library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity INTERFACE is
    port(
          enable: in std_logic;
          Xi: in std_logic_vector  (47 downto 0);
          Yi: in std_logic_vector  (47 downto 0);
          Zi: in std_logic_vector  (47 downto 0);
          Xo: out std_logic_vector (34 downto 0);
          Yo: out std_logic_vector (34 downto 0);
          Zo: out std_logic_vector (34 downto 0)
   	);
end entity;
   	
architecture INTF of INTERFACE is    
begin
   process(enable,Xi,Yi,Zi)
   begin
       if enable='0' then
          Xo <= Xi(34 downto 0);
          Yo <= Yi(34 downto 0);
          Zo <= Zi(34 downto 0);
       end if;
   end process;
end INTF;